v880最近宕机，最大化自检，求大侠帮忙看看

xiaozhi168

@(#)OBP 4.10.8 2003/07/25 08:42 Sun Fire 880
Online:  CPU0 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU1 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU2 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Executing Power On SelfTest w/%o0 = 0000.0000.0001.4041

0>@(#) Daktari POST 4.10.8 2003/07/24 18:05
       /export/common-source/firmware_re/post/post-build-4.10.8/Camelot/daktari/integrated  (firmware_re)  
0>Jump from OBP->POST.
0>CPUs present in system: 0 1 2 3
0>diag-switch? configuration variable set TRUE.
0>Diag level set to MAX.
0>MFG scrpt mode set NORM
0>I/O port set to serial TTYA.
0>
0>Start selftest...
0>Init CPU
0>      Cheetah_plus Version 11.0
0>DMMU Registers Access
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Probe Ecache
0>      Size = 00000000.00800000...
0>Ecache Data Bitwalk
0>Ecache Address Bitwalk
0>Scrub and Setup Ecache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test and Init Temp Mailbox
1>Init CPU
2>Init CPU
3>Init CPU
1>      Cheetah_plus Version 11.0
2>      Cheetah_plus Version 11.0
3>      Cheetah_plus Version 11.0
1>DMMU Registers Access
2>DMMU Registers Access
3>DMMU Registers Access
1>DMMU TLB DATA RAM Access
2>DMMU TLB DATA RAM Access
3>DMMU TLB DATA RAM Access
1>DMMU TLB TAGS Access
2>DMMU TLB TAGS Access
3>DMMU TLB TAGS Access
1>IMMU Registers Access
2>IMMU Registers Access
3>IMMU Registers Access
1>IMMU TLB DATA RAM Access
2>IMMU TLB DATA RAM Access
1>IMMU TLB TAGS Access
2>IMMU TLB TAGS Access
3>IMMU TLB DATA RAM Access
3>IMMU TLB TAGS Access
1>Probe Ecache
1>      Size = 00000000.00800000...
2>Probe Ecache
2>      Size = 00000000.00800000...
3>Probe Ecache
3>      Size = 00000000.00800000...
1>Ecache Data Bitwalk
2>Ecache Data Bitwalk
3>Ecache Data Bitwalk
1>Ecache Address Bitwalk
2>Ecache Address Bitwalk
3>Ecache Address Bitwalk
1>Scrub and Setup Ecache
2>Scrub and Setup Ecache
3>Scrub and Setup Ecache
1>Setup and Enable DMMU
2>Setup and Enable DMMU
3>Setup and Enable DMMU
1>Setup DMMU Miss Handler
2>Setup DMMU Miss Handler
3>Setup DMMU Miss Handler
1>Test and Init Temp Mailbox
2>Test and Init Temp Mailbox
3>Test and Init Temp Mailbox
0>Initializing Scan Database
0>Mask DAR errors off
0>Init MDR DTL
0>Init DAR DTL
0>Enable Partial DAR error
0>Init DCS DTL
0>Init I2C
0>Unquiesce Safari
0>Margin all voltages to nominal
0>Scan ring integrity
0>INFO: H/W under test = CPU Board Slot C (Cheetah 4, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot D (Cheetah 5, DCDS [0-7], SRAMs) Scan Ring NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot C (Cheetah 6, SRAMs) Scan Ring NOT Present or Shut OFF
0>INFO: H/W under test = CPU Board Slot D (Cheetah 7, SRAMs) Scan Ring NOT Present or Shut OFF
0>Set Trip Temp CPU 0 to 110C
0>Set Trip Temp CPU 1 to 110C
0>Set Trip Temp CPU 2 to 110C
0>Set Trip Temp CPU 3 to 110C
0>MON AUG  25 10:53:46 GMT 8
0>Safari quick check
0>       to IO-bridge_0
0>       to IO-bridge_1
0>Safari full  check
0>       to IO-bridge_0
0>       to IO-bridge_1
0>Disable Cheetah 0 error checking
0>Disable Cheetah 1 error checking
0>Disable Cheetah 2 error checking
0>Disable Cheetah 3 error checking
0>Probe and Setup Memory
0>INFO:    512MB Bank 0
0>INFO:    512MB Bank 1
0>INFO:    512MB Bank 2
0>INFO:    512MB Bank 3
0>
0>Data Bitwalk on Master
0>      Test Bank 0.
0>      Test Bank 1.
0>      Test Bank 2.
0>      Test Bank 3.
0>Address Bitwalk on Master
0>INFO: Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.20000000.
0>INFO: Addr walk mem test on CPU 0 Bank 1: 00000001.00000000 to 00000001.20000000.
0>INFO: Addr walk mem test on CPU 0 Bank 2: 00000002.00000000 to 00000002.20000000.
0>INFO: Addr walk mem test on CPU 0 Bank 3: 00000003.00000000 to 00000003.20000000.
0>Set Mailbox
0>Setup Final DMMU Entries
0>Post Image Region Scrub
0>Run POST from Memory
0>Verifying checksum on copied image.
0>The Memory's CHECKSUM value is 6791.
0>The Memory's Content Size value is 9410a.
0>Success...  Checksum on Memory Validated.
0>Safari quick check
0>       to IO-bridge_0
0>       to IO-bridge_1
0>Safari full  check
0>       to IO-bridge_0
0>       to IO-bridge_1
1>Safari quick check
1>       to IO-bridge_0
1>       to IO-bridge_1
1>Safari full  check
1>       to IO-bridge_0
1>       to IO-bridge_1
2>Safari quick check
2>       to IO-bridge_0
2>       to IO-bridge_1
2>Safari full  check
2>       to IO-bridge_0
2>       to IO-bridge_1
3>Safari quick check
3>       to IO-bridge_0
3>       to IO-bridge_1
3>Safari full  check
3>       to IO-bridge_0
3>       to IO-bridge_1
1>Probe and Setup Memory
2>Probe and Setup Memory
3>Probe and Setup Memory
1>INFO:    512MB Bank 0
1>INFO:    512MB Bank 1
1>INFO:    512MB Bank 2
1>INFO:    512MB Bank 3
1>
2>INFO:    512MB Bank 0
2>INFO:    512MB Bank 1
2>INFO:    512MB Bank 2
2>INFO:    512MB Bank 3
2>
3>INFO:    512MB Bank 0
3>INFO:    512MB Bank 1
3>INFO:    512MB Bank 2
3>INFO:    512MB Bank 3
3>
1>Set Mailbox
2>Set Mailbox
3>Set Mailbox
0>Data Bitwalk on Slave 1
0>      Test Bank 0.
0>      Test Bank 1.
0>      Test Bank 2.
0>      Test Bank 3.
0>Data Bitwalk on Slave 2
0>      Test Bank 0.
0>      Test Bank 1.
0>      Test Bank 2.
0>      Test Bank 3.
0>Data Bitwalk on Slave 3
0>      Test Bank 0.
0>      Test Bank 1.
0>      Test Bank 2.
0>      Test Bank 3.
0>Address Bitwalk on Slave 1
0>INFO: Addr walk mem test on CPU 1 Bank 0: 00000010.00000000 to 00000010.20000000.
0>INFO: Addr walk mem test on CPU 1 Bank 1: 00000011.00000000 to 00000011.20000000.
0>INFO: Addr walk mem test on CPU 1 Bank 2: 00000012.00000000 to 00000012.20000000.
0>INFO: Addr walk mem test on CPU 1 Bank 3: 00000013.00000000 to 00000013.20000000.
0>Address Bitwalk on Slave 2
0>INFO: Addr walk mem test on CPU 2 Bank 0: 00000020.00000000 to 00000020.20000000.
0>INFO: Addr walk mem test on CPU 2 Bank 1: 00000021.00000000 to 00000021.20000000.
0>INFO: Addr walk mem test on CPU 2 Bank 2: 00000022.00000000 to 00000022.20000000.
0>INFO: Addr walk mem test on CPU 2 Bank 3: 00000023.00000000 to 00000023.20000000.
0>Address Bitwalk on Slave 3
0>INFO: Addr walk mem test on CPU 3 Bank 0: 00000030.00000000 to 00000030.20000000.
0>INFO: Addr walk mem test on CPU 3 Bank 1: 00000031.00000000 to 00000031.20000000.
0>INFO: Addr walk mem test on CPU 3 Bank 2: 00000032.00000000 to 00000032.20000000.
0>INFO: Addr walk mem test on CPU 3 Bank 3: 00000033.00000000 to 00000033.20000000.
1>Setup Final DMMU Entries
2>Setup Final DMMU Entries
3>Setup Final DMMU Entries
1>Map Slave POST to master memory
2>Map Slave POST to master memory
3>Map Slave POST to master memory
1>8k DMMU TLB 0 Data
1>8k DMMU TLB 1 Data
2>8k DMMU TLB 0 Data
3>8k DMMU TLB 0 Data
0>8k DMMU TLB 0 Data
1>8k DMMU TLB 0 Tags
2>8k DMMU TLB 1 Data
3>8k DMMU TLB 1 Data
0>8k DMMU TLB 1 Data
1>8k DMMU TLB 1 Tags
2>8k DMMU TLB 0 Tags
3>8k DMMU TLB 0 Tags
0>8k DMMU TLB 0 Tags
1>8k IMMU TLB Data
2>8k DMMU TLB 1 Tags
3>8k DMMU TLB 1 Tags
0>8k DMMU TLB 1 Tags
1>8k IMMU TLB Tags
2>8k IMMU TLB Data
3>8k IMMU TLB Data
0>8k IMMU TLB Data
1>Instruction Cache Tag RAM
2>8k IMMU TLB Tags
3>8k IMMU TLB Tags
0>8k IMMU TLB Tags
1>Instruction Cache RAM
2>Instruction Cache Tag RAM
3>Instruction Cache Tag RAM
0>Instruction Cache Tag RAM
1>I-Cache Valid/Predict TAGS Test
2>Instruction Cache RAM
3>Instruction Cache RAM
0>Instruction Cache RAM
1>I-Cache Branch Predict Array Test
2>I-Cache Valid/Predict TAGS Test
3>I-Cache Valid/Predict TAGS Test
0>I-Cache Valid/Predict TAGS Test
1>Instruction Cache Snoop Tag Field
2>I-Cache Branch Predict Array Test
3>I-Cache Branch Predict Array Test
0>I-Cache Branch Predict Array Test
1>Flush D/W caches
2>Instruction Cache Snoop Tag Field
3>Instruction Cache Snoop Tag Field
0>Instruction Cache Snoop Tag Field
2>Flush D/W caches
3>Flush D/W caches
0>Flush D/W caches
1>Data Cache RAM
1>Data Cache Tags
2>Data Cache RAM
3>Data Cache RAM
1>Data Micro Tags
2>Data Cache Tags
3>Data Cache Tags
0>Data Cache RAM
1>D-Cache SnoopTags Test
2>Data Micro Tags
3>Data Micro Tags
0>Data Cache Tags
1>WCache RAM
2>D-Cache SnoopTags Test
3>D-Cache SnoopTags Test
0>Data Micro Tags
1>WCache Tags
2>WCache RAM
3>WCache RAM
0>D-Cache SnoopTags Test
1>W-Cache Valid bit Test
2>WCache Tags
3>WCache Tags
0>WCache RAM
1>W-Cache Bank valid bit Test
2>W-Cache Valid bit Test
3>W-Cache Valid bit Test
0>WCache Tags
1>W-Cache SnoopTAGS Test
2>W-Cache Bank valid bit Test
3>W-Cache Bank valid bit Test
0>W-Cache Valid bit Test
1>Prefetch Cache RAM
2>W-Cache SnoopTAGS Test
3>W-Cache SnoopTAGS Test
0>W-Cache Bank valid bit Test
1>Prefetch Cache Tags
2>Prefetch Cache RAM
3>Prefetch Cache RAM
0>W-Cache SnoopTAGS Test
1>P-Cache SnoopTags Test
2>Prefetch Cache Tags
3>Prefetch Cache Tags
0>Prefetch Cache RAM
1>P-Cache Status Data Test
2>P-Cache SnoopTags Test
3>P-Cache SnoopTags Test
0>Prefetch Cache Tags
1>Branch Prediction Initialization
2>P-Cache Status Data Test
3>P-Cache Status Data Test
0>P-Cache SnoopTags Test
2>Branch Prediction Initialization
3>Branch Prediction Initialization
0>P-Cache Status Data Test
0>Branch Prediction Initialization
1>Print Mem Config

xiaozhi168

1>Caches : Icache is ON, Dcache is ON, Wcache is OFF, Pcache is ON.
1>Memory in non-interleave config:
1>      Bank 0    512MB : 00000010.00000000 -> 00000010.20000000.
1>      Bank 1    512MB : 00000011.00000000 -> 00000011.20000000.
1>      Bank 2    512MB : 00000012.00000000 -> 00000012.20000000.
1>      Bank 3    512MB : 00000013.00000000 -> 00000013.20000000.
2>Print Mem Config
2>Caches : Icache is ON, Dcache is ON, Wcache is OFF, Pcache is ON.
2>Memory in non-interleave config:
2>      Bank 0    512MB : 00000020.00000000 -> 00000020.20000000.
2>      Bank 1    512MB : 00000021.00000000 -> 00000021.20000000.
2>      Bank 2    512MB : 00000022.00000000 -> 00000022.20000000.
2>      Bank 3    512MB : 00000023.00000000 -> 00000023.20000000.
3>Print Mem Config
3>Caches : Icache is ON, Dcache is ON, Wcache is OFF, Pcache is ON.
3>Memory in non-interleave config:
3>      Bank 0    512MB : 00000030.00000000 -> 00000030.20000000.
3>      Bank 1    512MB : 00000031.00000000 -> 00000031.20000000.
3>      Bank 2    512MB : 00000032.00000000 -> 00000032.20000000.
3>      Bank 3    512MB : 00000033.00000000 -> 00000033.20000000.
0>Print Mem Config
0>Caches : Icache is ON, Dcache is ON, Wcache is OFF, Pcache is ON.
0>Memory in non-interleave config:
0>      Bank 0    512MB : 00000000.00000000 -> 00000000.20000000.
0>      Bank 1    512MB : 00000001.00000000 -> 00000001.20000000.
0>      Bank 2    512MB : 00000002.00000000 -> 00000002.20000000.
0>      Bank 3    512MB : 00000003.00000000 -> 00000003.20000000.
1>Scrub Memory
2>Scrub Memory
3>Scrub Memory
0>Scrub Memory
1>Quick Block Mem Test
2>Quick Block Mem Test
3>Quick Block Mem Test
1>Quick Test 16777216 bytes at 00000010.00000000
2>Quick Test 16777216 bytes at 00000020.00000000
3>Quick Test 16777216 bytes at 00000030.00000000
0>Quick Block Mem Test
0>Quick Test 16777216 bytes at 00000000.00600000
0>40% Done...
1>Flush Caches
2>Flush Caches
3>Flush Caches
0>Flush Caches
0>IO-Bridge unit 0 init      test   
0>IO-Bridge unit 1 init      test   
0>IO-Bridge unit 0 reg       test   
0>IO-Bridge unit 0 mem       test   
0>IO-Bridge unit 0 PCI DMA A test   
0>IO-Bridge unit 0 PCI DMA B test   
0>IO-Bridge unit 0 PCI merg  test   
0>IO-Bridge unit 0 PCI iommu test   
0>IO-Bridge unit 0 PCI stc   test   
0>IO-Bridge unit 0 interrupt test   
0>IO-Bridge unit 1 reg       test   
0>IO-Bridge unit 1 mem       test   
0>IO-Bridge unit 1 PCI DMA C test   
0>IO-Bridge unit 1 PCI DMA D test   
0>IO-Bridge unit 1 PCI merg  test   
0>IO-Bridge unit 1 PCI iommu test   
0>IO-Bridge unit 1 PCI stc   test   
0>IO-Bridge unit 1 interrupt test   
1>IO-Bridge unit 0 init      test   
1>IO-Bridge unit 0 reg       test   
1>IO-Bridge unit 0 mem       test   
1>IO-Bridge unit 0 PCI DMA   test   
1>IO-Bridge unit 0 PCI merg  test   
1>IO-Bridge unit 0 PCI iommu test   
1>IO-Bridge unit 0 PCI stc   test   
1>IO-Bridge unit 0 interrupt test   
1>IO-Bridge unit 1 init      test   
1>IO-Bridge unit 1 reg       test   
1>IO-Bridge unit 1 mem       test   
1>IO-Bridge unit 1 PCI DMA   test   
1>IO-Bridge unit 1 PCI merg  test   
1>IO-Bridge unit 1 PCI iommu test   
1>IO-Bridge unit 1 PCI stc   test   
1>IO-Bridge unit 1 interrupt test   
2>IO-Bridge unit 0 init      test   
2>IO-Bridge unit 0 reg       test   
2>IO-Bridge unit 0 mem       test   
2>IO-Bridge unit 0 PCI DMA   test   
2>IO-Bridge unit 0 PCI merg  test   
2>IO-Bridge unit 0 PCI iommu test   
2>IO-Bridge unit 0 PCI stc   test   
2>IO-Bridge unit 0 interrupt test   
2>IO-Bridge unit 1 init      test   
2>IO-Bridge unit 1 reg       test   
2>IO-Bridge unit 1 mem       test   
2>IO-Bridge unit 1 PCI DMA   test   
2>IO-Bridge unit 1 PCI merg  test   
2>IO-Bridge unit 1 PCI iommu test   
2>IO-Bridge unit 1 PCI stc   test   
2>IO-Bridge unit 1 interrupt test   
3>IO-Bridge unit 0 init      test   
3>IO-Bridge unit 0 reg       test   
3>IO-Bridge unit 0 mem       test   
3>IO-Bridge unit 0 PCI DMA   test   
3>IO-Bridge unit 0 PCI merg  test   
3>IO-Bridge unit 0 PCI iommu test   
3>IO-Bridge unit 0 PCI stc   test   
3>IO-Bridge unit 0 interrupt test   
3>IO-Bridge unit 1 init      test   
3>IO-Bridge unit 1 reg       test   
3>IO-Bridge unit 1 mem       test   
3>IO-Bridge unit 1 PCI DMA   test   
3>IO-Bridge unit 1 PCI merg  test   
3>IO-Bridge unit 1 PCI iommu test   
3>IO-Bridge unit 1 PCI stc   test   
3>IO-Bridge unit 1 interrupt test   
1>FPU Registers and Data Path
2>FPU Registers and Data Path
3>FPU Registers and Data Path
0>FPU Registers and Data Path
1>FPU Move Registers
2>FPU Move Registers
3>FPU Move Registers
0>FPU Move Registers
1>FSR Read/Write
2>FSR Read/Write
3>FSR Read/Write
0>FSR Read/Write
1>FPU Branch Instructions
2>FPU Branch Instructions
3>FPU Branch Instructions
0>FPU Branch Instructions
1>FPU Functional Test
2>FPU Functional Test
3>FPU Functional Test
0>FPU Functional Test
1>FPU BLOCK REG TEST
2>FPU BLOCK REG TEST
3>FPU BLOCK REG TEST
0>FPU BLOCK REG TEST
1>Calculating memory test time
2>Calculating memory test time
3>Calculating memory test time
0>Calculating memory test time
1>INFO: The expected TIMEOUT for the block memory tests can exceed 2 minutes.
2>INFO: The expected TIMEOUT for the block memory tests can exceed 2 minutes.
3>INFO: The expected TIMEOUT for the block memory tests can exceed 2 minutes.
0>INFO: The expected TIMEOUT for the block memory tests can exceed 2 minutes.
1>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 140 minutes.
2>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 140 minutes.
3>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 140 minutes.
0>INFO: The expected TIMEOUT for the MOVI memory tests can exceed 140 minutes.
1>Block Memory
2>Block Memory
3>Block Memory
0>Block Memory
1>Test 536870912 bytes on bank 0....
2>Test 536870912 bytes on bank 0....
3>Test 536870912 bytes on bank 0....
0>Test 530579456 bytes on bank 0....
0>1% Done...
0>4% Done...
0>6% Done...
0>9% Done...
0>12% Done...
0>15% Done...
0>18% Done...
0>20% Done...
0>23% Done...
0>26% Done...
0>29% Done...
0>32% Done...
0>35% Done...
0>37% Done...
0>40% Done...
0>43% Done...
0>46% Done...
0>49% Done...
0>51% Done...
0>54% Done...
0>57% Done...
0>60% Done...
0>63% Done...
0>65% Done...
0>68% Done...
0>71% Done...
0>74% Done...
0>77% Done...
0>79% Done...
0>82% Done...
0>85% Done...
0>88% Done...
0>91% Done...
0>94% Done...
1>Test 536870912 bytes on bank 1....
2>Test 536870912 bytes on bank 1....
0>96% Done...
3>Test 536870912 bytes on bank 1....
0>99% Done...
0>Test 536870912 bytes on bank 1....
0>1% Done...
0>4% Done...
0>6% Done...
0>9% Done...
0>12% Done...
0>15% Done...
0>18% Done...
0>20% Done...
0>23% Done...
0>26% Done...
0>29% Done...
0>31% Done...
0>34% Done...
0>37% Done...
0>40% Done...
0>43% Done...
0>45% Done...
0>48% Done...
0>51% Done...
0>54% Done...
0>56% Done...
0>59% Done...
0>62% Done...
0>65% Done...
0>68% Done...
0>70% Done...
0>73% Done...
0>76% Done...
0>79% Done...
0>81% Done...
0>84% Done...
0>87% Done...
2>Test 536870912 bytes on bank 2....
0>90% Done...
1>Test 536870912 bytes on bank 2....
3>Test 536870912 bytes on bank 2....
0>93% Done...
0>95% Done...
0>98% Done...
0>Test 536870912 bytes on bank 2....
0>1% Done...
0>4% Done...
0>6% Done...
0>9% Done...
0>12% Done...
0>15% Done...
0>18% Done...
0>20% Done...
0>23% Done...
0>26% Done...
0>29% Done...
0>31% Done...
0>34% Done...
0>37% Done...
0>40% Done...
0>43% Done...
0>45% Done...
0>48% Done...
0>51% Done...
0>54% Done...
0>56% Done...
0>59% Done...
0>62% Done...
0>65% Done...
0>68% Done...
0>70% Done...
0>73% Done...
0>76% Done...
0>79% Done...
0>81% Done...
0>84% Done...
2>Test 536870912 bytes on bank 3....
1>Test 536870912 bytes on bank 3....
3>Test 536870912 bytes on bank 3....
0>87% Done...
0>90% Done...
0>93% Done...
0>95% Done...
0>98% Done...
0>Test 536870912 bytes on bank 3....
0>1% Done...
0>4% Done...
0>6% Done...
0>9% Done...
0>12% Done...
0>15% Done...
0>18% Done...
0>20% Done...
0>23% Done...
0>26% Done...
0>29% Done...
0>31% Done...
0>34% Done...
0>37% Done...
0>40% Done...
0>43% Done...
0>45% Done...
0>48% Done...
0>51% Done...
0>54% Done...
0>56% Done...
0>59% Done...
0>62% Done...
0>65% Done...
0>68% Done...
0>70% Done...
0>73% Done...
0>76% Done...
0>79% Done...
0>81% Done...
0>84% Done...
0>87% Done...
0>90% Done...
0>93% Done...
0>95% Done...
0>98% Done...
0>
0>Motherboard/Centerplane Board Part Number:   
0>      5016323-05-52
0>IO/Riser Board Part Number:   
0>      5015142-19-52
0>CPUA Board Part Number:   
0>      5016163-02-53
0>CPUB Board Part Number:   
0>      5016163-02-53
0>CPUC Board Part Number:   
0>INFO: Unpopulated Slot
0>CPUD Board Part Number:   
0>INFO: Unpopulated Slot
0>Turn IO-Bridge 0 errors on
0>Turn IO-Bridge 1 errors on
0>Turn Cheetah 0 errors on
0>Turn Cheetah 1 errors on
0>Turn Cheetah 2 errors on
0>Turn Cheetah 3 errors on
0>Turn Module A DCDS errors on
0>Turn Module B DCDS errors on
0>Turn DCS errors on
0>Turn DAR errors on
0>Turn error traps on
0>INFO:
0>      POST Passed all devices.
0>POST: Return to OBP.


CPU0: System Power On Selftest Completed
    Pass/Fail Status  = 0000.0000.0000.0000
    ESB Overall Status  = ffff.ffff.ffff.ffff


<*>
POST Reset

@(#)OBP 4.10.8 2003/07/25 08:42 Sun Fire 880
Online:  CPU0 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU1 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU2 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Configuring CPUs..........
... CPU0 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU1 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU2 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00
... CPU3 Rated Speed 1050MHz, Safari 150MHz, want 7:1, got 7:1 ==> CPU 1050MHz
         Ecache 8MB 3.3ns mode=4-4-4 2-way ECCR: 0000.0000.0323.4c00 Done
<*>
CPU Configuration Reset

@(#)OBP 4.10.8 2003/07/25 08:42 Sun Fire 880
Online:  CPU0 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU1 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online:  CPU2 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Online: *CPU3 Ultra-III+ (v11.0) 7:1 1050MHz 8MB 4:1 ECache
Enabling Safari .......... CPU0 CPU1 CPU2 CPU3 Done
Probing Memory............
Probing CPU0 memory configuration
  NGDIMM#0 part# 501-5401-03 serial# B0QPB8,  128MB + 128MB,  SC#0
  NGDIMM#1 part# 501-5401-03 serial# B0QS3B,  128MB + 128MB,  SC#0
  NGDIMM#2 part# 501-5401-03 serial# B0QS3N,  128MB + 128MB,  SC#0
  NGDIMM#3 part# 501-5401-03 serial# B0QS3M,  128MB + 128MB,  SC#0
  NGDIMM#4 part# 501-5401-03 serial# B0QPCN,  128MB + 128MB,  SC#0
  NGDIMM#5 part# 501-5401-03 serial# B0QPCR,  128MB + 128MB,  SC#0
  NGDIMM#6 part# 501-5401-03 serial# B0QPCM,  128MB + 128MB,  SC#0
  NGDIMM#7 part# 501-5401-03 serial# B0QPCQ,  128MB + 128MB,  SC#0
Probing CPU1 memory configuration
  NGDIMM#0 part# 501-5401-03 serial# B0QS3F,  128MB + 128MB,  SC#0
  NGDIMM#1 part# 501-5401-03 serial# B0QVCH,  128MB + 128MB,  SC#0
  NGDIMM#2 part# 501-5401-03 serial# B0QS31,  128MB + 128MB,  SC#0
  NGDIMM#3 part# 501-5401-03 serial# B0QS30,  128MB + 128MB,  SC#0
  NGDIMM#4 part# 501-5401-03 serial# B0QS2S,  128MB + 128MB,  SC#0
  NGDIMM#5 part# 501-5401-03 serial# B0QS10,  128MB + 128MB,  SC#0
  NGDIMM#6 part# 501-5401-03 serial# B0QS8H,  128MB + 128MB,  SC#0
  NGDIMM#7 part# 501-5401-03 serial# B0QS33,  128MB + 128MB,  SC#0
Probing CPU2 memory configuration
  NGDIMM#0 part# 501-5401-03 serial# B0QS3C,  128MB + 128MB,  SC#0
  NGDIMM#1 part# 501-5401-03 serial# B0QS37,  128MB + 128MB,  SC#0
  NGDIMM#2 part# 501-5401-03 serial# B0QPD6,  128MB + 128MB,  SC#0
  NGDIMM#3 part# 501-5401-03 serial# B0QPCF,  128MB + 128MB,  SC#0
  NGDIMM#4 part# 501-5401-03 serial# B0QPCS,  128MB + 128MB,  SC#0
  NGDIMM#5 part# 501-5401-03 serial# B0QPBC,  128MB + 128MB,  SC#0
  NGDIMM#6 part# 501-5401-03 serial# B0QPCL,  128MB + 128MB,  SC#0
  NGDIMM#7 part# 501-5401-03 serial# B0QPCK,  128MB + 128MB,  SC#0
Probing CPU3 memory configuration
  NGDIMM#0 part# 501-5401-03 serial# B0QVCK,  128MB + 128MB,  SC#0
  NGDIMM#1 part# 501-5401-03 serial# B0QVCM,  128MB + 128MB,  SC#0
  NGDIMM#2 part# 501-5401-03 serial# B0QS35,  128MB + 128MB,  SC#0
  NGDIMM#3 part# 501-5401-03 serial# B0QS34,  128MB + 128MB,  SC#0
  NGDIMM#4 part# 501-5401-03 serial# B0QS38,  128MB + 128MB,  SC#0
  NGDIMM#5 part# 501-5401-03 serial# B0QS39,  128MB + 128MB,  SC#0
  NGDIMM#6 part# 501-5401-03 serial# B0QS2T,  128MB + 128MB,  SC#0
  NGDIMM#7 part# 501-5401-03 serial# B0QS2Y,  128MB + 128MB,  SC#0
Mungeing Memory...........Done
HiMem: 0000.00b0.0000.0000, size: 0000.0001.0000.0000
Configuring Memory........ CPU0 CPU1 CPU2 CPU3 Done
Init ICache/etc........... CPU0 CPU1 CPU2 CPU3 Done
Init ECache Tags.......... CPU0 CPU1 CPU2 CPU3 Done
Clearing TLBs............. CPU0 CPU1 CPU2 CPU3 Done
Setup I/DTLBs............. CPU0 CPU1 CPU2 CPU3 Done
Enabling Cache/MMUs....... CPU0 CPU1 CPU2 CPU3 Done
Init ECache Data.......... CPU0 CPU1 CPU2 CPU3 Done
Zeroing memory...Done
Copying FLASHRAM to memory...Verifying base 96KB...Done
Jumping into RAM (leaving slave CPUs in ROM)
RAM CRC = 0000.0000.49d5.45ea;  ROM CRC = 0000.0000.49d5.45ea
Dropping in...
Find dropin, Decompressing Done, Size 0000.0000.0007.7fd0 (480KB)
Slave CPUs starting Forth at 0000.0000.f000.00e0
Boot  CPU3 starting Forth at 0000.0000.f000.00e0

ttya initialized
Probing gptwo at 0,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 1,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 2,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 3,0 SUNW,UltraSPARC-III+ (1050 MHz @ 7:1, 8 MB)
   memory-controller
Probing gptwo at 4,0 Nothing there
Probing gptwo at 5,0 Nothing there
Probing gptwo at 6,0 Nothing there
Probing gptwo at 7,0 Nothing there
Probing gptwo at 8,0 pci pci
Probing gptwo at 9,0 pci pci
Loading Support Packages: kbd-translator obp-tftp SUNW,i2c-ram-device
   SUNW,fru-device
Loading onboard drivers: ebus flashprom bbc power i2c fru fru fru fru
   fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru
   fru fru fru fru fru fru fru fru fru fru fru fru fru fru fru i2c
   controller smbus-ara controller temperature temperature temperature
   ioexp temperature adio adio ioexp ioexp ioexp ioexp ioexp ioexp
   ioexp adio adio adio adio temperature-sensor fru fru fru fru fru fru
   rscrtc hotplug-controller hotplug-controller hotplug-controller
   hotplug-controller bbc i2c i2c nvram idprom rtc gpio pmc rsc-control
   rsc-console serial
Memory Configuration:
CPU0 Bank0  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #0
CPU0 Bank1  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #2
CPU0 Bank2  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #4
CPU0 Bank3  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #6
CPU1 Bank0  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #0
CPU1 Bank1  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #2
CPU1 Bank2  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #4
CPU1 Bank3  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #6
CPU2 Bank0  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #1
CPU2 Bank1  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #3
CPU2 Bank2  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #5
CPU2 Bank3  128 +  128 +  128 +  128 :  512MB @  a000000000  8-way #7
CPU3 Bank0  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #1
CPU3 Bank1  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #3
CPU3 Bank2  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #5
CPU3 Bank3  128 +  128 +  128 +  128 :  512MB @  b000000000  8-way #7
Probing /pci@8,600000 Device 1  network
Probing /pci@8,600000 Device 2  SUNW,qlc fp disk
Probing /pci@8,700000 Device 1  scsi disk tape
Probing /pci@8,700000 Device 2  Nothing there
Probing /pci@8,700000 Device 3  Nothing there
Probing /pci@8,700000 Device 4  Nothing there
Probing /pci@8,700000 Device 5  SUNW,XVR-100
Probing /pci@9,600000 Device 1  lpfc sd Cannot Init Link.
***   FCode LP9000 PCI_Bus (lpfc) Version 1.13a2   ***

Probing /pci@9,600000 Device 2  lpfc sd ***   FCode LP9000 PCI_Bus (lpfc) Version 1.31a5   ***


Probing /pci@9,700000 Device 1  network usb
Probing /pci@9,700000 Device 2  Nothing there
Probing /pci@9,700000 Device 3  Nothing there
Probing /pci@9,700000 Device 4  pci
Probing /pci@9,700000/pci@4 Device 0  pci108e,1000 SUNW,qfe
Probing /pci@9,700000/pci@4 Device 1  pci108e,1000 SUNW,qfe
Probing /pci@9,700000/pci@4 Device 2  pci108e,1000 SUNW,qfe
Probing /pci@9,700000/pci@4 Device 3  pci108e,1000 SUNW,qfe
Probing /pci@9,700000/pci@4 Device 4  Nothing there
Probing /pci@9,700000/pci@4 Device 5  Nothing there
Probing /pci@9,700000/pci@4 Device 6  Nothing there
Probing /pci@9,700000/pci@4 Device 7  Nothing there
Probing /pci@9,700000/pci@4 Device 8  Nothing there
Probing /pci@9,700000/pci@4 Device 9  Nothing there
Probing /pci@9,700000/pci@4 Device a  Nothing there
Probing /pci@9,700000/pci@4 Device b  Nothing there
Probing /pci@9,700000/pci@4 Device c  Nothing there
Probing /pci@9,700000/pci@4 Device d  Nothing there
Probing /pci@9,700000/pci@4 Device e  Nothing there
Probing /pci@9,700000/pci@4 Device f  Nothing there

Snowict

POST完全正常。
宕机可能原因：1。 MEMORY 2。 CPU 3。APPLICATION。
发些宕机的信息上来

xiaozhi168

Nov 30 04:20:40 ss7-sd-1 cl_eventlogd[569]: [ID 848580 daemon.error] Restarting on signal 1.
Dec  1 13:29:27 ss7-sd-1 SC[SUNWscsyb.monitor]:syb-grp:syb-res: [ID 392998 local7.error] Fault monitor probe response time exceeded timeout (60 secs). The timeout for subsequent probes will be temporarily increased by 10%
Dec  1 13:29:27 ss7-sd-1 SC[SUNWscsyb.monitor]:syb-grp:syb-res: [ID 564643 local7.error] Fault monitor detected error TIMEOUT_ERROR: 1 DEFAULT Action=NONE : A timeout has occured - DBMS appears to be slow
Dec  1 13:30:21 ss7-sd-1 SC[SUNWscsyb.monitor]:syb-grp:syb-res: [ID 589805 local7.error] Fault monitor probe response times are back below 50% of probe timeout. The timeout will be reduced to it's configured value
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2305 to CLARiiON CK200040500596 port B1.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 1 to CK200040500596 is dead.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 4 to CK200040500596 is dead.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 2 to CK200040500596 is dead.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 3 to CK200040500596 is dead.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 0 to CK200040500596 is dead.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 7 to CK200040500596 is dead.
Dec  1 21:30:48 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 1 to CK200040500596 is alive.
Dec  1 21:30:48 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 4 to CK200040500596 is alive.
Dec  1 21:30:48 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 2 to CK200040500596 is alive.
Dec  1 21:30:48 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 3 to CK200040500596 is alive.
Dec  1 21:30:48 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 0 to CK200040500596 is alive.
Dec  1 21:30:48 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 7 to CK200040500596 is alive.
Dec  1 21:30:48 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is alive.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2305 to CLARiiON CK200040500596 port B1.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 3 to CK200040500596 is dead.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 4 to CK200040500596 is dead.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 2 to CK200040500596 is dead.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 0 to CK200040500596 is dead.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 7 to CK200040500596 is dead.
Dec  1 22:27:01 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 1 to CK200040500596 is dead.
Dec  1 22:32:02 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 3 to CK200040500596 is alive.
Dec  1 22:32:02 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 4 to CK200040500596 is alive.
Dec  1 22:32:02 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 2 to CK200040500596 is alive.
Dec  1 22:32:02 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 0 to CK200040500596 is alive.
Dec  1 22:32:02 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 7 to CK200040500596 is alive.
Dec  1 22:32:02 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 1 to CK200040500596 is alive.
Dec  1 22:32:02 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is alive.
Dec  1 22:34:12 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Volume 6006016044321000617C98119F93D811 is unbound.
Dec  1 22:34:12 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 1 Lun 4 to CK200040500596 is dead.
Dec  1 22:34:12 ss7-sd-1 md_stripe: [ID 641072 kern.warning] WARNING: md: dbvg/d103: read error on /dev/did/dsk/d12s0
Dec  1 22:34:12 ss7-sd-1 last message repeated 1 time
Dec  1 22:34:12 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: 6006016044321000617C98119F93D811 is alive.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2304 to CLARiiON CK200040500596 port B0.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 1 to CK200040500596 is dead.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 0 to CK200040500596 is dead.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 7 to CK200040500596 is dead.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 3 to CK200040500596 is dead.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 2 to CK200040500596 is dead.
Dec  1 22:41:03 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 4 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2305 to CLARiiON CK200040500596 port B1.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 3 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 7 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 4 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 1 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 2 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 0 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2304 Tgt 0 Lun 5 to CK200040500596 is alive.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2304 to CLARiiON CK200040500596 port B0.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is alive.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2305 to CLARiiON CK200040500596 port B1.
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2304 Tgt 0 Lun 5 to CK200040500596 is alive.
Dec  1 22:41:08 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2304 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 22:41:08 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2304 to CLARiiON CK200040500596 port B0.
Dec  1 22:41:08 ss7-sd-1 emcp: [ID 801593 kern.notice] Info: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is alive.
Dec  1 22:41:09 ss7-sd-1 SUNW,UltraSPARC-III+: [ID 548282 kern.warning] WARNING: [AFT1] Bus Error (BERR) Event detected by CPU0 Privileged Data Access at TL=0, errID 0x0000b74c.88d968b8
Dec  1 22:41:09 ss7-sd-1     AFSR 0x00100800<RIV,BERR>.00000000 AFAR 0x000007fb.00106000
Dec  1 22:41:09 ss7-sd-1     Fault_PC 0x1035034
Dec  1 22:41:10 ss7-sd-1 unix: [ID 836849 kern.notice]
Dec  1 22:41:10 ss7-sd-1 ^Mpanic[cpu0]/thread=2a10052bd40:
Dec  1 22:41:11 ss7-sd-1 unix: [ID 768234 kern.notice] [AFT1] errID 0x0000b74c.88d968b8 BERR Error(s)
Dec  1 22:41:11 ss7-sd-1     See previous message(s) for details
Dec  1 22:41:12 ss7-sd-1 unix: [ID 100000 kern.notice]
Dec  1 22:41:13 ss7-sd-1 genunix: [ID 723222 kern.notice] 000002a10052b060 SUNW,UltraSPARC-III+:cpu_aflt_log+5c0 (2a10052b16b, 1, 2a10052b378, 10, 117a3e0, 117a40
Dec  1 22:41:14 ss7-sd-1 genunix: [ID 179002 kern.notice]   %l0-3: 0000000000000000 0000000000000010 0000000000000003 000002a10052b378
Dec  1 22:41:14 ss7-sd-1   %l4-7: 000007fb00106000 0000000000000000 000002a10052b2a8 000002a10052b11e
Dec  1 22:41:16 ss7-sd-1 genunix: [ID 723222 kern.notice] 000002a10052b2b0 SUNW,UltraSPARC-III+:cpu_deferred_error+4d4 (0, 1, 4010080003200000, 40100800, 7fb, 7fbff877)
Dec  1 22:41:17 ss7-sd-1 genunix: [ID 179002 kern.notice]   %l0-3: 000002a10052b378 0000000400000000 4010080003200000 000003000310e928
Dec  1 22:41:17 ss7-sd-1   %l4-7: 0000000000000001 000002a10052b8c0 000002a102fe7aa0 0000000080000000
Dec  1 22:41:18 ss7-sd-1 genunix: [ID 723222 kern.notice] 000002a10052b810 unix:ktl0+48 (30002a80870, 300003d2000, 0, 0, 1400, 2a10052bd40)
Dec  1 22:41:19 ss7-sd-1 genunix: [ID 179002 kern.notice]   %l0-3: 0000000000000003 0000000000001400 0000008800001602 000000000116ef00
Dec  1 22:41:19 ss7-sd-1   %l4-7: 0000000001447fd8 0000000000000000 0000000000000006 000002a10052b8c0
Dec  1 22:41:21 ss7-sd-1 genunix: [ID 723222 kern.notice] 000002a10052b960 lpfc:fc_intr+b4 (30002a8c000, b, 0, 30002a8c000, 0, 30002a8c27
Dec  1 22:41:22 ss7-sd-1 genunix: [ID 179002 kern.notice]   %l0-3: 0000000000000000 00000300003d2000 ffffffff7d800400 0000030002a8c278
Dec  1 22:41:22 ss7-sd-1   %l4-7: 00000000811029c0 00000000810ff800 0000000000000000 00000000810db400
Dec  1 22:41:24 ss7-sd-1 genunix: [ID 723222 kern.notice] 000002a10052baa0 pcisch:pci_intr_wrapper+74 (30002a5f588, 244, 30003090000, 2a10052bd40, 4880, 131e22c)
Dec  1 22:41:25 ss7-sd-1 genunix: [ID 179002 kern.notice]   %l0-3: 000000000136e680 00000300007a0918 0000000000000000 0000000000000000
Dec  1 22:41:25 ss7-sd-1   %l4-7: 00000300003959a8 0000000000000000 000000007811a800 000000007811a800
Dec  1 22:41:27 ss7-sd-1 unix: [ID 100000 kern.notice]
Dec  1 22:41:27 ss7-sd-1 genunix: [ID 672855 kern.notice] syncing file systems...
Dec  1 22:41:32 ss7-sd-1 genunix: [ID 733762 kern.notice]  4
Dec  1 22:41:33 ss7-sd-1 genunix: [ID 904073 ker

xiaozhi168

会不会是cpu出问题了？

Snowict

从PANIC信息看可能是PCI卡或者是PCI插槽有问题。综合CLUSTER的错误，人为是EMC的FC-HBA问题。更换之。

killer911

已经提示
Dec  1 22:41:06 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is dead.

ibmlenovo

Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 0 Lun 5 to CK200040500596 is dead.
Dec  1 21:26:37 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Killing bus 2305 to CLARiiON CK200040500596 port B1.
Dec  1 22:34:12 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Volume 6006016044321000617C98119F93D811 is unbound.
Dec  1 22:34:12 ss7-sd-1 emcp: [ID 801593 kern.notice] Error: Path Bus 2305 Tgt 1 Lun 4 to CK200040500596 is dead.
Dec  1 22:34:12 ss7-sd-1 md_stripe: [ID 641072 kern.warning] WARNING: md: dbvg/d103: read error on /dev/did/dsk/d12s0
Dec  1 22:34:12 ss7-sd-1 last message repeated 1 time


WARNING: [AFT1] Bus Error (BERR) Event detected by CPU0 Privileged Data Access at TL=0, errID 0x0000b74c.88d968b8

我认为是 与存储 断接导致的。

xiaozhi168

存储接的是emc CX600  最近控制器电池没电了， 莫非是主机光纤卡有问题么？
但是启动后查看主机状态正常的，而且链路也没问题，会是数据库引起的么？

lei8c8

EMC CLARiiON与主机连接有问题
toubleshooting path: host HBA --> cabling --> SAN switch port status --> FC switch zone --> EMC controller