- 论坛徽章:
- 3
|
对于其原因,我的电脑截图不知为什么出了问题,所以无法截图了.有兴趣的用modelsim仿真一下以下的电路,仔细对照一下波形图,再想想或许就明白了.
- `timescale 1ns/1ps
- module reset_module_test(
- gpio,
- clk,
- rst,
- io_out
- );
- input gpio,clk,rst;
- output io_out;
- parameter REG_WILDTH=6;
- reg io_out;
- reg [REG_WILDTH-1:0]gpio_reg;
- wire negedge_gpio, posedge_gpio;
- assign negedge_gpio = (&(gpio_reg[REG_WILDTH-1:REG_WILDTH/2])) & (!(|(gpio_reg[REG_WILDTH/2-1:0])));
- assign posedge_gpio = (!(|(gpio_reg[REG_WILDTH-1:REG_WILDTH/2]))) & (&(gpio_reg[REG_WILDTH/2-1:0]));
- always@(posedge rst or posedge clk)
- if(rst)
- gpio_reg <= 0;
- else
- gpio_reg <= {gpio_reg[REG_WILDTH-2:0], gpio};
-
- always@(posedge rst or posedge clk)
- if(rst)
- io_out <= 1'b0;
- else
- begin
- if(negedge_gpio)
- io_out <= 1'b0;
- else if(posedge_gpio)
- io_out <= 1'b1;
- end
- endmodule
- module testbench
- ();
- reg clk,gpio,rst;
- wire io_out;
- reset_module_test reset_module_inst(
- gpio,
- clk,
- rst,
- io_out
- );
- initial
- forever
- begin
- clk=0;
- #2.5;
- clk=1;
- #2.5;
- end
-
- initial
- begin
- rst=0;
- #7;
- rst=1;
- #20;
- rst=0;
- end
-
- initial
- begin
- gpio = 1;
- #1000;
- gpio=0;
- #100;
- gpio=1;
- #2000;
- gpio=0;
- #99;
- gpio=1;
- #4000;
- gpio=0;
- #12;
- gpio=1;
- #4000;
- gpio=0;
- #5;
- gpio=1;
- #2;
- gpio=0;
- #7;
- gpio=1;
- #6;
- gpio=0;
- #197;
- gpio=1;
- #5000;
- $display("OK!");
- $stop();
- end
- endmodule
复制代码 |
|