分类： 嵌入式
2010-08-04 14:22:07
input signed [7:0] a, b; output signed [15:0] o; assign o = a * b; input [7:0] a, b; output [15:0] o; wire signed [15:0] o_sgn; assugb o_sgn = $signed(a) * $signed(b); assign o = $unsigned(o_sgn);
input signed [7:0] a, b; input signed [8:0] o; assign o = a + b; // Verilog會自動進行符號的擴展。
input [7:0] a;
input signed [7:0] b;
output signed [15:0] o;
// Don't do this: assign o = a * b;
// The $signed({1'b0, a}) can convert the unsigned number to signed
number.
assign o = $signed({1'b0, a}) * b;
input signed [7:0] a;
output signed [15:0] o;
// Don't do this: assign o = a * 8'b10111111;
// Use $signed() system task
assign o = a * $signed(8'b10111111);
// or sb keyword.
assign o = a * 8'sb10111111;
input signed [7:0] a; input signed [7:0] b; output signed [15:0] o1, o2; // Don't do this: assign o1 = a[7:0]; assign o1 = a; // Don't do this: assign o2 = a[6:0] * b; assign o2 = $signed(a[6:0]) + b |
